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AD7741–SPECIFICATIONS T
(V DD = +4.75 V to +5.25 V; V REF = +2.5 V; f CLKIN = 6.144 MHz; all specifications T MIN to
MAX unless otherwise noted.)
B and Y Version 1
Parameter
2
Min Typ Max
Units
Conditions/Comments
DC PERFORMANCE
Integral Nonlinearity
f CLKIN = 200 kHz 3
f CLKIN = 3 MHz 3
f CLKIN = 6.144 MHz
Offset Error
± 0.012
± 0.012
± 0.024
± 40
% of Span 4
% of Span
% of Span
mV
V DD > 4.8 V
Gain Error
Offset Error Drift 3
Gain Error Drift 3
Power Supply Rejection Ratio 3
0
+0.8
± 30
± 16
–63
+1.6
% of Span
μ V/ ° C
ppm of Span/ ° C
dB
? V DD = ± 5%
ANALOG INPUT 5
Input Current
Input Voltage Range
0
± 50
± 100
V REF
nA
V
+2.5 V REFERENCE (REFIN/OUT)
REFIN
Nominal Input Voltage
Input Impedance 6
REFOUT
2.5
N/A
V
Output Voltage
Output Impedance 3
Reference Drift 3
Line Rejection
Reference Noise (0.1 Hz to 10 Hz) 3
2.38
2.50
1
± 50
–60
100
2.60
V
k ?
ppm/ ° C
dB
μ V p-p
LOGIC OUTPUT
Output High Voltage, V OH
Output Low Voltage, V OL
Minimum Output Frequency
Maximum Output Frequency
4.0
0.05 f CLKIN
0.45 f CLKIN
0.4
V
V
Hz
Hz
Output Sourcing 800 μ A 7
Output Sinking 1.6 mA 7
V IN = 0 V
V IN = V REF
LOGIC INPUT
PD ONLY
Input High Voltage, V IH
Input Low Voltage, V IL
Input Current
2.4
0.8
± 100
V
V
nA
Pin Capacitance
6
10
pF
CLKIN ONLY
Input High Voltage, V IH
Input Low Voltage, V IL
Input Current
3.5
0.8
± 2
V
V
μ A
Pin Capacitance
6
10
pF
CLOCK FREQUENCY
Input Frequency
6.144
MHz
For Specified Performance
POWER REQUIREMENTS
V DD
4.75
5.25
V
I DD (Normal Mode)
I DD (Power-Down)
Power-Up Time 3
15
30
8
35
mA
μ A
μ s
Output Unloaded
Coming Out of Power-Down Mode
Temperature ranges: B Version –40 ° C to +85 ° C: Y Version: –40 ° C to +105 ° C.
NOTES
1
2
3
4
5
6
7
See Terminology.
Guaranteed by design and characterization, not production tested.
Span = Maximum Output Frequency–Minimum Output Frequency.
The absolute voltage on the input pin must not go more positive than V DD – 2.25 V or more negative than GND.
Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400 μ A in order to overdrive the internal reference.
These logic levels apply to CLKOUT only when it is loaded with one CMOS load.
Specifications subject to change without notice.
–2 –
REV. 0
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